The invention relates to improvements in microprocessor chips for enhancing the construction and operation of computer equipment.
Microprocessor chips as presently constructed have various operational performance limits in the handling of different types of logic data. When such limits are exceeded, problems occur such as overshoot, poor signal quality, electromagnetic interference, reflections, crosstalk noise, etc. With respect to CMOS logic, for example, the clock rates are relatively slow as compared to those available for ECL logic circuitry. However, ECL logic circuitry have a lower circuit density and a higher cost factor. Accordingly, new and more expensive packaging would be required for high speed circuit boards utilizing microprocessor chips embodying ECL logic circuitry for high speed performance. Also facilities for handling correspondingly high power levels are required for such high speed performance as compared to lower power levels for the lower clock rates associated with CMOS logic circuitry.
It is therefore an important object of the present invention to provide an improved high speed microprocessor chip embodying CMOS, ECL or BiCMOS logic circuitry which will provide cost and performance gains for each of the different types of logic circuitry as well as to provide greater peripheral computer integration than was heretofore deemed possible.